One type of prior art non-volatile computer memory is the erasable programmable read-only memory ("EPROM"). The EPROM can be programmed by a user. Once programmed, the EPROM retains its data until erased. Erasure of an EPROM with ultraviolet light erases the entire contents of the memory. The memory may then be reprogrammed with new data.
One type of prior art EPROM is the 27C256 complementary high-performance metal oxide semiconductor ("CHMOS") EPROM manufactured by Intel Corporation of Santa Clara, Calif., which is 256 Kilobit (32 Kilobit by 8 bit) 5 volt EPROM. The 27C256 EPROM includes an address buffer to receive addresses from address input pins of the EPROM. Addresses stored in the address buffer are decoded in a decoding circuit to address the memory array of the device. The device also includes a chip enable pin .sup.CE and output enable pin .sup.OE, which are the two control function pins.
That EPROM has a plurality of normal operating modes. Those normal operating modes include a read mode, a programming mode, and a standby mode. For the read mode, a logic low signal is applied to both the chip enable pin and the output enable pin. This permits data stored in the EPROM to be read out as addressed. Addresses are provided at the address pins to access the data stored in the memory array.
A programming mode allows data to be stored by the EPROM. To enter the programming mode, a logical high signal is applied to the output enable .sup.OE pin, a logical low signal is applied to the chip enable .sup.CE pin and a 12 volt high voltage is applied to a Vpp pin of the EPROM. Once in the programming mode, then data applied to the EPROM is stored in memory cells of the EPROM at addresses provided from the address input pins.
A standby mode is entered by applying a logical high voltage at the chip enable pin .sup.CE of the device. Power consumption of the EPROM is substantially reduced in the standby mode.
When the EPROM operates in one of the normal operating modes, the address input pins receive addresses that are only used to address data. Each of the addresses includes a set of binary bits. Each bit is either a logical zero or a logical one.
Before certain prior art EPROMs are shipped by at least one manufacturer, a series of tests are conducted to determine whether the EPROMs meet product specifications. Some tests relate to individual cells in the memory array. For one such test, a high voltage is applied over the oxide layer of a cell to stress the cell in order to detect whether the layer breaks down under such high voltage. Another is to apply a significantly high voltage to the gate or drain of a cell to detect whether the content of the cell, when programmed, is erased under such high voltage. The EPROMs not meeting the specifications are rejected.
In order to facilitate the tests, certain prior art EPROMs include a set of test modes. Each test mode is designated for at least one test operation. The various functions of the device are tested by the test modes. Some of the test modes test the internal configuration of the EPROM.
One category of prior art EPROM typically has about 25 to 100 test modes. A logical high voltage for the input pins of that EPROM is approximately 2 volts, and a logical low voltage for the input pins of that EPROM is approximately 0.8 volts. A certain desired test mode is triggered in one type of the prior art EPROM device by applying a high voltage of approximately 12 volts to a certain one of the address input pins. The applied high voltage of 12 volts is then received by a test mode detection and trigger circuit and the desired test mode is triggered by the circuit. The applied high voltage of 12 volts remains on the particular address input pin to maintain the test mode. The high voltage of 12 volts is significantly higher than the logical high voltage of 2 volts so that the test mode detection and trigger circuit with the EPROM can distinguish the high voltage from a logical high signal. If the high voltage of 12 volts is applied to a different address input pin of the EPROM, then a different test model is initiated. When an individual cell is tested, the address on the address pins of the EPROM is used to locate the particular cell.
An end user of certain prior art EPROM is typically unaware of the test modes of the EPROM. Those test modes are typically not referenced by the data sheets that the end user sees. In addition, normal operation of the EPROM typically does not require that the end user use the test modes. In particular, an end user typically would have no occasion to apply a high voltage of 12 volts to any of the address pins of the EPROM. Therefore, it is typically stated that the test modes of the EPROM are transparent to the end user.
One disadvantage of the prior art way of using single address pins to trigger test modes is that the address pin to which the high voltage of 12 volts is applied to trigger the test mode cannot simultaneously be used for the purpose of addressing a data location. In other words, that pin used for triggering the test mode loses its "addressing" function during the test mode. Thus, not all memory locations are addressable during the test mode that uses the an address pin to trigger the test mode. Nevertheless, it would be advantageous for certain tests that the entire memory array be addressable during those tests.